Computer Architecture - Hw Reorder Buffer Final One

Computer Architecture - Hw Reorder Buffer Final One - Transcript

Re Order Buffer Trace Homework

CSCE 513 Fall 2010 October 12 2010

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CSCE 513 Fall 2010

I have attached a powerpoint slide that I would like for you to fill out and submit on Tuesday I would like four cycle times Cycle 2 Cycle 4 Cycle 6 and Cycle 8 for each of these show the status at the end of the cycle Note INCLUDE the DADDIU and the BNE as the newer OoOE machines do you can either add an integer unit or just ignore that that is not part of the diagram on the powerpoint but include them in the analysis i e insert them in the ROB

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CSCE 513 Fall 2010

HW ROB problem
For HW I would like for you to walk through the example see Figure 2 16 for a later stage Loop L D F0 0 R1 MUL D F4 F0 F2 S D F4 0 R1 DADDIU R1 R1 8 BNE R1 R2 Loop branches if R1 R2

I have attached a powerpoint slide that I would like for you to fill out and submit on Tuesday
3 CSCE 513 Fall 2010

Latency Assumptions
Instruction Load Float add Float Multiply Store Latency cycles 1 2 6 1

Also assume Also issue and execute on separate cycles Execute and write CDB on separate cycles When writing to ROB on CDB everything else can When CSCE 513 Fall 2010 4 read also read

Dest

Instruction
L D F0 0 R1

Issue
1

Execute

Value

Ready

ROB
Example pp 108
Cycle

F0

No

1

From Memory Dest Addr Dest Addr
rob 1 F0 0 Reg R1 0 R R1

Registers

To Memory

Dest Op

Vj Qj

Vk Qk Dest Op Vj Qj Vk Qk

Int adder
Reg
ROB

FP multipler
F6 F8 F10 F12 F14

F0 1

F2

F4

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CSCE 513 Fall 2010
Busy

yes

Dest

Instruction
L D F0 0 R1 MUL D F4 F0 F2

Issue
1 2

Execute 2

Value

Ready

ROB
Example pp 108
Cycle

F0 F4

No No

2

From Memory Dest Addr
rob 1 0 Reg R1

Registers

To Memory

Dest Op

Vj Qj

Vk Qk Dest Op
rob 2 MUL D

Vj Qj
rob 1

Vk Qk
Regs F2

Int adder
Reg
ROB

FP multipler
F6 F8 F10 F12 F14

F0 1 yes

F2

F4 2

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CSCE 513 Fall 2010
Busy

yes

Dest

Instruction
L D F0 0 R1 MUL D F4 F0 F2 S D F4 0 R1

Issue
1 2 3

Execute 2

Value
Mem 0 Reg R1

Ready

ROB
Example pp 108
Cycle

F0 F4 0 Regs R1

Yes No No

3

From Memory Dest Addr Addr
F0 0 R R1

Registers

To Memory rob 2 0 Re R1

Dest Op

Vj Qj

Vk Qk Dest Op
rob 2 MUL D

Vj Qj
Mem 0 Reg R1

Vk Qk
Regs F2

Int adder
Reg
ROB

FP multipler
F6 F8 F10 F12 F14

F0 1 yes

F2

F4 2

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CSCE 513 Fall 2010
Busy

yes

Dest

Instruction
L D F0 0 R1 MUL D F4 F0 F2 S D F4 0 R1 DADDIU R1 R1 8

Issue
1 2 3 4

Execute 2 4 9

Value
Mem 0 Regs R1

Ready

ROB
Example pp 108
Cycle

F0 F4 0 Regs R1 R1

Yes
commit

No No No

4

From Memory Dest Addr

Registers
F0 Mem 0 Regs R1

To Memory rob 2 0 Reg R1

Dest Op
rob 4 Add

Vj Qj
Regs R1

Vk Qk
8

Dest Op
2 MUL D

Vj Qj
Mem 0 Reg R1

Vk Qk
Regs F2

Int adder
Reg
ROB

FP multipler
F6 F8 F10 F12 F14

F0

F2

F4 2

8

CSCE 513 Fall 2010
Busy

no

yes

Dest

Instruction
L D F0 0 R1 MUL D F4 F0 F2 S D F4 0 R1 DADDIU R1 R1 8 BNE

Issue
1 2 3 4 5

Execute 2 4 9

Value
Mem 0 Regs R1

Ready

ROB
Example pp 108
Cycle

F0 F4 0 Regs R1 R1

Yes No No

5

No

5

From Memory Dest Addr

Registers

To Memory rob 2 0 Reg R1

Dest Op
rob 4 Add

Vj Qj
Regs R1

Vk Qk
8

Dest Op
2 MUL D

Vj Qj
Mem 0 Reg R1

Vk Qk
Regs F2

Int adder
Reg
ROB

FP multipler
F6 F8 F10 F12 F14

F0

F2

F4 2

9

CSCE 513 Fall 2010
Busy

no

yes

Dest

Instruction
L D F0 0 R1 MUL D F4 F0 F2 S D F4 0 R1 DADDIU R1 R1 8 BNE R1 R2 Loop

Issue
1 2 3 4 5 6

Execute 2 4 9 4 5 6

Value
Mem 0 Regs R1

Ready

ROB
Example pp 108
Cycle
head

F0 F4 0 Regs R1 R1

Yes No No

Regs R1 8

Yes

6

F0

L D F0 0 R1

From Memory Dest Addr
rob 6 0 R R1 8

Registers

To Memory rob 2 0 Reg R1

Dest Op

Vj Qj

Vk Qk Dest Op
2 MUL D

Vj Qj
Mem 0 Regs R1

Vk Qk
Regs F2

Int adder
Reg
ROB

FP multipler
F6 F8 F10 F12 F14

F0

F2

F4 2

10

CSCE 513 Fall 2010
Busy

no

yes

Dest

Instruction
L D F0 0 R1 MUL D F4 F0 F2 S D F4 0 R1 DADDIU R1 R1 8 BNE R1 R2 Loop

Issue
1 2 3 4 5 6 7

Execute 2 4 9 4 5 7 7

Value
Mem 0 Regs R1

Ready

ROB
Example pp 108
Cycle

F0 F4 0 Regs R1 R1

Yes Yes

2 Regs R1 8

Yes Yes Yes No No

7

F0 F4

L D F0 0 R1 MUL D F4 F0 F2

From Memory Dest Addr

Registers

To Memory rob 2 0 Reg R1

Dest Op

Vj Qj

Vk Qk Dest Op
2 MUL D

Vj Qj
Mem 0 Regs R1

Vk Qk
Regs F2

Int adder
Reg
ROB

FP multipler
F6 F8 F10 F12 F14

F0 6 yes

F2

F4 7

11

CSCE 513 Fall 2010
Busy

yes

Dest

Instruction
S D F4 0 R1 MUL D F4 F0 F2 S D F4 0 R1 DADDIU R1 R1 8 BNE R1 R2 Loop

Issue
8 2 3 4 5 6 7

Execute

Value

Ready

ROB
Example pp 108
Cycle

0 Regs R1 F4 0 Regs R1 R1

No 4 9 4 5 7 7 8 1 Regs F2 2 Regs R1 8 Yes Yes Yes Yes No No

8

F0 F4

L D F0 0 R1 MUL D F4 F0 F2

From Memory Dest Addr

Registers

To Memory rob 2 0 Reg R1

1 Regs F2
Dest Op Vj Qj Vk Qk Dest Op
2 MUL D

Vj Qj
Mem 0 Regs R1

Vk Qk
Regs F2

Int adder
Reg
ROB

FP multipler
F6 F8 F10 F12 F14

F0 6 yes

F2

F4 7

12

CSCE 513 Fall 2010
Busy

yes

Dest

Instruction
S D F4 0 R1 MUL D F4 F0 F2 S D F4 0 R1 DADDIU R1 R1 8 BNE R1 R2 Loop

Issue
8 2 3 4 5 6 7

Execute

Value

Ready

ROB
Example pp 108
Cycle

0 Regs R1 F4 0 Regs R1 R1

No 4 9 4 5 7 7 8 1 Regs F2 2 Regs R1 8 Yes Yes Yes Yes No No

9

F0 F4

L D F0 0 R1 MUL D F4 F0 F2

From Memory Dest Addr

Registers

To Memory rob 2 0 Reg R1

Dest Op

Vj Qj

Vk Qk Dest Op
2 MUL D

Vj Qj
Mem 0 Regs R1

Vk Qk
Regs F2

Int adder
Reg
ROB

FP multipler
F6 F8 F10 F12 F14

F0 6 yes

F2

F4 7

13

CSCE 513 Fall 2010
Busy

yes