CAD for VLSI Design-2 Lecture-9
1 of 10
CAD for VLSI Design-2 Lecture-9
Featured
A Time of Social Change
Adding Zero
THE REALITY OF SIN
Austria Hungary and the Ottoman Empire
Regression Wisdom
On Building Robust Web Service Based Application
investment module
Development and Validation of a measure of emotional
Goods Market Variables
WarOf1812
ancient india and china
Categorization of Common Coupling and Its Application to the Maintainability of the Linux Kernel
Introduction to Information Security - Access Control
Constant Functions
Theology 2 Movie Review Jericho
shell write up1
Farkas and Wetauer How CEOs lead
PLEASE DO NOT THROW YOUR TRASH ON THE FLOOR
Promoting Business Environment
The Goof4
CAD for VLSI Design-2 Lecture-9 - Transcript
CAD for VLSI Design II
Lecture 9 V Kamakoti and Shankar Balachandran
Overview of this Lecture
Delay elements in CMOS circuits Cont d
Clock Frequency
The limiting factor on the clocking rate is the propagation delay through the IFL block
Changes on the Q s must propagate through the IFL before they can affect the next state
Timing Violations
Tc l k tC Q max t f f max t s umax
The clock period Tclk has a lower bound of tff max If the clock period is equal to tff max tC Q max then the flip flop state changes can violate setup times Remedy Use faster flip flops decrease tC Q Use faster gates decrease tff Use a slower clock increase clock period Tclk
Clock Skew
The previous discussion assumes that clock signals arrive at all flip flops simultaneously this is not a good assumption since it is not true in practice Because of different wire lengths over which the clock signals travel and the load at the destination there is a slight difference in clock arrival times at different flip flop inputs Clock skew tskew is the difference in time between triggering edges seen at different flip flops Clock skew affects minimum Tclk
Timing Analysis Example
For the circuit given below determine all the sequential circuit timing parameters
For a D flip flop use tsu 2ns th 15ns and tC Q 20ns For a NAND gate use tp max 10ns and tp min 3ns
tif max 3t p max nand 30ns tif min 2t p min nand 6ns t ff max 2t p max nand 20ns t ff min 2t p min nand 6ns tc max 2t p max nand 20ns tc min 2t p min nand 6ns
Tsu tsu max tif max tc min 2 30 6 26ns Th th max tif min tc max 20 15 6 29ns Tclk tC Q max t ff max tsu max 20 20 2 42ns f clk max 1 42ns 23 8MHz tskew max tC Q min t ff min th max 20 6 15 11ns
For a D flip flop use tsu 2ns th 15ns tC Q 20ns For a NAND gate use tp max 10ns tp min 3ns
1 Phase Clock w Level Triggering
t w td q min tlmin th max t skewmax t skewmax
and
tlmin t w td q min th max t skewmax
d q min
t
t w t sumax or
tlmin t w th max
References
UTD 3325 Course Material University of Texas at Dallas
Questions and Answers
Thank You












