CAD for VLSI Design-1 Lecture-22

CAD for VLSI Design-1 Lecture-22 - Transcript

CAD for VLSI Design I
Lecture 22 V Kamakoti and Shankar Balachandran

Overview of this Lecture
Examples of Logic Synthesis of HDL constructs Technology Cell Library Design Constraints
Area Power and Timing

Simple Examples
assign out a b c

a b out c

Simple Examples
assign out a b c If all are 2 bit vectors
a 0 b 0 out 0 c 0 a 1 b 1 c 1 out 1

Simple Examples
assign c out sum a b c in yields a Full adder assign out s i1 i0 yields a 2 to 1 multiplexer Always the construct yields a multiplexer if s out i1 else out i0 has the same effect

Simple Examples
case s 1 b0 out i0 1 b1 out i1 endcase yields the same result Large case statements may be used to infer large multiplexers

Simple Examples
The for loops may be used to form cascaded combinational logic c c in for i 0 i 7 i i 1 c sum i a i b i c c out c 8 bit ripple adder

Simple Examples
always statement infers both sequential and combinational circuits always posedge clk q d This is a flipflop always clk or d if clk q d This is a latch

Simple Examples
always a or b or c in c out sum a b c in This yields a full adder The function statement synthesize to combinational blocks with one output variable The output may be a scalar or a vector

Simple Examples
function 4 0 fulladd input 3 0 a b input c in begin fulladd a b c in end endfunction

RTL Description Translation Unoptimized Intermediate Representation Logic Optimization Technology Mapping and Optimization Design Constraints

Standard Cell Library Technology dependent

Optimized Gate level Representation

Synthesis Design Flow

Technology Library
Comprises of cells Each cell has to be characterized What is Cell Characterization
Functionality of the cell Area of the cell layout Timing information about the cell Power information about the cell

Cells are characterized by the fab vendors

Design Constraints
Timing
The circuit must meet certain timing requirements static timing analyzer

Area
The area of the final layout must not exceed a limit

Power
The power dissipation in the circuit must not exceed a threshold

Area Vs Timing
Faster circuits are big why

Area

timing

Area Vs Timing
The design has to be parallelized for better timing and hence more area

Operating Environment Factors
Input and output delays drive strengths and loads will affect the optimization for the target technology

Synthesis Flow
Very high speed circuits the designers may do the cell characterization rather than the fab vendors In normal scenario translation logic optimization and technology mapping are done internally in the logic synthesis and are not visible to the designer Efficient RTL and specifying design constraints correctly are very crucial

Synthesis for Submicron Designs
Interconnect delays become dominant in the overall delays As geometries shrink synthesis tools will need to have a tighter link to layout right at the RTL level in order to accurately model interconnect delays Timing analyzers built into synthesis tools will have to account for interconnect delays in the total delay calculation

References
Chapter 14 Samir Palnitkar Verilog HDL

Questions and Answers

Thank You